Resistive memory devices including selected reference memory cells and methods of operating the same

ABSTRACT

A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean Patent Application No.2005-0107178, filed in the Korean Intellectual Property Office on Nov.9, 2005, the disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and, moreparticularly, to resistive memory devices.

BACKGROUND

It is known that some random access non-volatile memory devices canstore data by altering the resistance of the memory cells therein. Suchdevices are commonly referred to as resistive random access memories(ReRam). In operation, a ReRam memory cell can be programmed by changingthe resistance of the cell. For example, a logical data value of zerocan be programmed by changing the resistance of the cell to a relativelylow value, whereas as a logical data value of one can be programmed bychanging the resistance of the cell to a relatively high value.

One type of ReRam is a magnetic random access memory (MRAM), whichcombines semi-conductor electronics and magnetics. In MRAMs, the spin ofan electron, rather than the charge, can be used to indicate whether thedata stored in the cell is a logical data value of one or zero.

One type of architecture used in MRAMs provides conductive lines thatextend perpendicular to one another so that the conductive linesintersect with one another (sometimes referred to as a cross-pointarrangement). The cells used to store data are positioned at theintersections of the perpendicular conductive lines and can beconfigured as a magnetic tunnel junction (MTJ) device that is accessedusing an access transistor.

Data can be stored in a cell of the cross-point MRAM by generating acurrent in each of the conductive lines that intersect at the data cell.In particular, each of the currents flowing in the intersectingconductive lines can generate respective magnetic fields which, whencombined, can affect the alignment of the magnetic moment provided bythe MTJ, which can alter the resistance of the cell. For example, afirst combination of magnetic fields generated by the intersectingcurrents can orient the magnetic moment in a first direction so that theresistance offered by the cell corresponds to a logical data value of 0.In contrast, a second combination of magnetic fields can generate anopposing magnetic moment so that the resistance of the cell is alteredto indicate a logical data value of 1. Accordingly, data can be writtento the cells of the MRAM by causing currents to flow in intersectingconductive lines to change the resistance offered by the cell whenaccessed.

FIG. 1 illustrates an equivalent circuit including a conventionalcross-point MRAM where data cells are located at intersections ofwordlines (WL1-3) and bitlines (BL1-4). According to FIG. 1, a data cellC_(s) located at the intersection of BL2 and WL2 can be written bygenerating respective currents I_(WL) and I_(BL). The currents I_(WL)and I_(BL) both generate respective magnetic fields (the “hard” magneticfield and the “easy” magnetic field) in the data cell to be written. Theparticular combination of the magnitudes and directions of the H_(hard)and H_(easy) magnetic fields can cause the resistance of the data cellto be altered. The directions of the magnetic fields H_(hard) andH_(easy), are based on the directions of the currents I_(WL) and I_(BL).

Furthermore, ideally the magnetic fields generated by the current I_(WL)at the remaining intersections (BL1, 3, and 4) are insufficient, bythemselves, to alter the resistance of those remaining cells. It isdesirable to use the combined affect of the easy and hard magneticfields on the data cell so that the write operation to data cell C_(s)may be achieved. In other words, FIG. 1 shows that a magnetic fieldsH_(hard) is generated in the remaining cells due t-o the current I_(WL)even those remaining cells are not selected for programming. If themagnetic field H_(hard) for the unselected memory cells were sufficientto change the state of the unselected data cells, the data storedtherein may be unintentionally modified during the write of the selecteddata cell C_(s).

FIG. 2 shows a range of asteroidal graphs indicating variations inmagnetic fields that can affect the resistance of different MRAM cellsdue to process variations in manufacturing the MRAMs. In particular,FIG. 2 illustrates the different possible combined magnetic fieldsneeded to program data to a particular MRAM data cell. As shown in FIG.2, a first asteroidal curve AC1 indicates that a first MRAM data cellcan be programmed by any combination of the H_(hard) and H_(easy)magnetic fields on the curve. It will be understood that the termsH_(hard) and H_(easy) refer to the magnetic fields generated in the longand short directions of the data cell, respectively. The asteroidalcurve AC2 is shifted to the right relative to the asteroidal curve AC1and represents a second MRAM data cell which (because of processvariation) is programmed according to different H_(hard) and H_(easy)magnetic fields. Accordingly, in order to ensure that data can beprogrammed to any of the cells in the MRAM represented in FIG. 2, theH_(hard) and H_(easy) magnetic fields applied should be in the areareferred to as “Write Margin” in FIG. 2. In other words, because ofprocess variations, a worse case assumption may be made regarding theH_(hard) and H_(easy) magnetic fields that may be needed to programdata. Therefore, as shown in FIG. 2, if the asteroidal curve AC2reflects a “worst case” operation for a data cell in the MRAM, the MRAMoperates with a relatively narrow write margin.

Although both the H_(hard) and H_(easy) magnetic fields are usuallyapplied to a data cell in order to accomplish a write operation, it ispossible to program a data cell using only one of these magnetic fields.For example, as shown in FIG. 2, the first asteroidal curve AC1 showsthat if the corresponding data cell is written with, for example, aneasy magnetic field that exceeds He′, the state of the data cell may bechanged without any contribution of the hard magnetic field Hh′.

FIG. 3 is an equivalent diagram showing, what is referred to as asimultaneous write operation. In particular, a group of data cells C_(s)can be programmed by applying a current I_(WL) to WL2 and currentsI_(BL1-4) to bitlines BL1-BL4. As shown in FIG. 3, the combination ofthe respected easy and hard magnetic fields generated for each of theprogrammed data cells included in C_(s) operates to change theresistance of the data cells C_(s). As shown in FIG. 4, this type ofsimultaneous write operation can provide for additional write margin asthe same hard magnetic field is provided to each of the commonlyselected data cells included in C_(s).

Once data is programmed to the MRAM, the data may be read throughbiasing of selected data cells so that the respective resistances ofthose data cells may be evaluated to determine the data stored therein.In particular, different bias voltages may be applied across data cells(using the respective bitlines and wordlines/digitlines) to cause acurrent to flow to/from the selected data cell. The associatedresistance of the data cell can be determined based on the generatedcurrent.

The structure and operation of magnetic random access memories is alsodiscussed in, for example, U.S. Pat. No. 6,839,269 to Iwata et al. andU.S. Pat. No. 6,504,751 to Poechmueller.

SUMMARY

In some embodiments according to the invention, a resistive memorydevice can be read by applying a predetermined voltage level to a firstword line coupled to a first resistive memory cell during a readoperation of a second resistive memory cell that is coupled to a secondwordline. For example, in an operation where a first group of memorycells is to be simultaneously read from a block, a first voltage levelcan be applied to wordlines of memory cells that are not selected forthe read operation whereas a second voltage can be applied to thewordline that is coupled to the memory cells that are selected for theread operation.

Furthermore, the bitlines coupled to the resistive memory cells (bothselected as well as the non-selected) can have the first voltage levelapplied thereto so that the unselected memory cells are non-biased dueto the fact that the associated bitline and wordline for each of theunselected memory cells has substantially the same voltage appliedthereto. In contrast, the memory cells that are selected for the readare biased by the different voltages applied to the bitlines andwordlines of the selected memory cells. The non-biasing of theunselected memory cells can avoid the generation of parasitic currentswhich may otherwise increase/decrease the current generated by biasingof the selected memory cells. If unaddressed, the parasitic currents cantherefore affect operation of sense amplifier circuits which (if theparasitic currents are significant enough) cause errors during the readoperation.

In still other embodiments according to the invention, current used toprogram resistive memory cells in a block of the device can be conductedacross a single block of resistive memory cells to be programmed.Accordingly, the programming current may be conducted to the block to beprogrammed by conducting the programming current between adjacent blocksof resistive memory cells to a first current source transistor that islocated on a first opposing side of the block of resistive memory cellsto be programmed. The first current source transistor is used totransfer the programming current from the area between the adjacentblocks of resistive memory cells to across the block of memory cells tobe programmed. Furthermore, a second current source transistor islocated opposite the first current source transistor and is locatedbetween the block of the resistive memory cells to be programmed and afurther adjacent block of resistive memory cells which are not to beprogrammed.

The second current source transistor can conduct the programming currentaway from the block of resistive memory cells to be programmed in thearea that separates the adjacent resistive memory block. Accordingly,conducting the programming currents using the two opposing currentsource transistors allows the programming current to be conducted acrossbitlines in the block of resistive memory cells to be programmed whileavoiding conducting the programming current across bitlines included inadjacent blocks of resistive memory cells that are not to be programmed.Avoiding conducting the programming current across the bitlines ofresistive memory cells that are not to be programmed can reduce thelikelihood of disturbing the data stored in the resistive memory cellswhich are not to be programmed, thereby reducing the likelihood of anerror for a read of the disturbed resistive memory cells.

In other embodiments according to the invention, a resistive memorydevice can include first and second bias circuits that are configured toapply voltage levels to both selected as well as unselected wordlinesduring a read operation. For example, in some embodiments according tothe invention, a first bias circuit can be used to generate a voltagelevel that is applied to the wordlines connected to resistive memorycells that are to be read, whereas a second bias circuit can be used togenerate the second voltage level as applied to the wordlines coupled tothe memory cells that are not to be read.

In other embodiments according to the invention, a resistive memorydevice includes a plurality of cell blocks. Each of the cell blocks caninclude a plurality of bitlines and a plurality of bottom electrodesthat cross over the bitlines. A plurality of resistive cells are locatedat cross points of the bottom electrodes and the bitlines. Each of theresistive cells has a first electrode that is coupled to one of thebitlines and a second electrode coupled to one of the bottom electrodes.A plurality of digitlines correspond to each of the bottom electrodesand a plurality of switching transistors are coupled to the digitlinesand bottom electrodes. A cell block select line is coupled to an inputnode of the switching transistors, wherein at least one digitline iscoupled to each cell block in common.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit illustrating a cross-point configurationof a conventional MRAM.

FIG. 2 is a graphical representation of asteroidal curves for data cellsin a conventional MRAM.

FIG. 3 is an equivalent circuit of a conventional MRAM programmed usinga simultaneous write operation.

FIG. 4 is a graphical representation of asteroidal curves for data cellsin a conventional MRAM and an associated write margin programmed using asimultaneous write operation.

FIG. 5 is an equivalent circuit showing a cross-point configuration ofdata cells in an MRAM accessed by a read operation according to someembodiments of the invention.

FIG. 6 is an equivalent circuit of a cross-point configuration of datacells in an MRAM programmed using a simultaneous write operationaccording to some embodiments of the invention.

FIG. 7 is a schematic illustration of an MRAM including first and secondbias circuits and current source transistors according to someembodiments of the invention.

FIG. 8 is a simplified circuit schematic showing current sourcetransistors according to some embodiments of the invention.

FIG. 9 is a cross-sectional view of the simplified circuit shown inFIGS. 7 and 8.

FIGS. 10 and 11 are plan views of the circuit illustrated by FIGS. 7through 9.

FIG. 12 is a layout diagram for the simplified circuit schematicillustrated by FIGS. 7 through 11.

FIG. 13 is a block diagram of an MRAM including first and second biascircuits and current source transistors according to some embodiments ofthe invention.

FIG. 14 is a high-level block diagram illustrating systems includingMRAMs according to some embodiments in the invention.

FIG. 15 is a timing diagram illustrating read and program operations ofMRAMS according to some of the embodiments of the invention.

DESCRIPTION OF THE EMBODIMENTS ACCORDING TO THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. Like numbers refer to like elements throughout. As used herein theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. Thus, a first element could be termed a secondelement without departing from the teachings of the present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

In some embodiments according to the invention, a resistive memorydevice can be read by applying a predetermined voltage level to a firstword line coupled to a first resistive memory cell during a readoperation of a second resistive memory cell that is coupled to a secondwordline. For example, in an operation where a first group of memorycells is to be simultaneously read from a block, a first voltage levelcan be applied to wordlines of memory cells that are not selected forthe read operation, whereas a second voltage can be applied to thewordline that is coupled to the memory cells that are selected for theread operation.

Furthermore, the bitlines coupled to the resistive memory cells (bothselected as well as the nonselected) can have the first voltage levelapplied thereto so that the unselected memory cells are substantiallynon-biased due to the fact that the associated bitline and wordline foreach of the unselected memory cells has substantially the same voltageapplied thereto. In contrast, the memory cells that are selected for theread are biased by the different voltages applied to the bitlines andwordlines of the selected memory cells. The non-biasing of theunselected memory cells may avoid the generation of parasitic currentswhich may otherwise increase/decrease the current generated by biasingof the selected memory cells. If unaddressed, the parasitic currentscan, therefore, affect operation of sense amplifier circuits which (ifthe parasitic currents are significant enough) cause errors during theread operation.

In still other embodiments according to the invention, current used toprogram resistive memory cells in a block of the device can be conductedacross a single block of resistive memory cells to be programmed. Theprogramming current may be provided to the block to be programmed byconducting the programming current between adjacent blocks of resistivememory cells to a first current source transistor that is located on afirst opposing side of the block of resistive memory cells to beprogrammed. The first current source transistor is used to transfer theprogramming current from the area between the adjacent blocks ofresistive memory cells to across the block of memory cells to beprogrammed. Furthermore, a second current source transistor is locatedopposite the first current source transistor and is located between theblock of the resistive memory cells to be programmed and a furtheradjacent block of resistive memory cells which are not to be programmed.

The second current source transistor can conduct the programming currentaway from the block of resistive memory cells to be programmed in thearea that separates the adjacent resistive memory block. Accordingly,conducting the programming currents using the two opposing currentsource transistors allows the programming current to be conducted acrossbitlines in the block of resistive memory cells to be programmed whileavoiding conducting the programming current across bitlines included inadjacent blocks of resistive memory cells that are not to be programmed.Avoiding conducting the programming current across the bitlines ofresistive memory cells that are not to be programmed can reduce thelikelihood of disturbing the data stored in the resistive memory cellswhich are not to be programmed, thereby reducing the likelihood of anerror for a read of the disturbed resistive memory cells.

In other embodiments according to the invention, a resistive memorydevice can include first and second bias circuits that are configured toapply voltage levels to both selected as well as unselected wordlinesduring a read operation. For example, in some embodiments according tothe invention, a first bias circuit can be used to generate a voltagelevel that is applied to the wordlines connected to resistive memorycells that are to be read, whereas a second bias circuit can be used togenerate the second voltage level applied to the wordlines coupled tothe memory cells that are not to be read. Although many of theembodiments described herein reference MRAM devices, embodimentsaccording to the invention can also be provided for other types ofresistive memory devices, such as PRAMs and OxRAMs.

FIG. 5 is an equivalent circuit diagram illustrating a block ofresistive memory cells having biasing applied thereto during asimultaneous read operation in some embodiments according to theinvention. In particular, a block of resistive memory cells 500 includesresistive memory cells R_(m) arranged in rows and columns. The rows ofresistive memory cells R_(m) are coupled to respective bottom electrodesignal lines (BE1-M) which also correspond to wordlines used to accessthe rows of the resistive memory cells R_(m). The columns of theresistive memory cells R_(m) are coupled to respective bitlines (BL1-n)which are also coupled to respective sense amplifier circuits SA1-n.According to FIG. 5, the sense amplifier circuits SA1-n provide outputdata based on a comparison of a bias voltage (V_(b)) and a referencevoltage provided by a reference circuit Cr. A read operation can becarried out using the signal levels shown in FIG. 15 in some embodimentsaccording to the invention.

In operation, a first voltage level is applied to a row of resistivememory cells via the respective bottom electrode signal line BE1-m. Asecond voltage level is provided to each of the bitlines BL1-n for whicha resistive memory cell is to be accessed. Therefore, a voltage isprovided across each of the resistive memory cells R_(m) that is to beaccessed during the simultaneous read operation. The biasing across theaccessed resistive memory cells R_(m) provides for a current inproportion with the resistance provided by each of the accessedresistive memory cells R_(m). The logical data value stored within eachof the resistive memory cells R_(m) can be determined based on thecurrent/resistance associated with each of the resistive memory cellsR_(m) in response to the biasing.

In some embodiments according to the invention, the biasing provided tothe bitlines BL1-n is also provided to the bottom electrode signal linesof cells that are not selected for access during the read operation. Forexample, as shown in FIG. 5, a group of resistive memory cells C₂ isaccessed during the simultaneous read operation by providing biasing tothe bottom electrode signal line BE2 and to each of the remaining bottomelectrode signal lines BE. It will be understood that the voltage levelsprovided to the bottom electrode signal line BE2 and to the bitlinesBL1-n are different from one another so that a bias can be providedacross each of the resistive memory cells in the group C₂. As furthershown in FIG. 5, the groups of resistive memory cells C₁-C_(m)(excluding the group C₂) are provided with the same voltage levels viathe bottom electrode signal lines and the bitlines connected thereto.

In particular, the group C1 of resistive memory cells that is not to beaccessed during the read operation is provided with substantially equalbiasing by the bottom electrode signal line BE1 and the bitline BL1-n.Similarly, the group of resistive memory cells Cm which is not beaccessed during the read operation is provided with substantially equalvoltage levels at both the bottom electrode signal line M and therespective bitlines BL1-n. The substantially equal voltage levelsprovided across the unselected resistive memory cells in groups C₁-C_(m)(excluding the group C₂) provides substantially non-biasing so that anyparasitic currents generated by the unselected resistive memory cellscan be reduced. Otherwise, any parasitic currents generated by floatingof unselected resistive memory cells may affect the currents generatedby the biasing across the selected resistive memory cells, which in turnmay cause read errors due to the addition/subtraction of the parasiticcurrents to/from the currents generated by the biasing across theselected resistive memory cells C_(p).

It will be understood that the voltage level provided to the bottomelectrode signal line coupled to the resistive memory cells to be readcan be greater than or less than the biasing provided by the bitlinesBL1-n. It will be further understood that the bottom electrode signallines BE1-m can be equivalent to wordlines W/L1-m.

FIG. 6 is an equivalent circuit diagram shown in FIG. 5 during asimultaneous write operation in some embodiments according to theinvention. In particular, the simultaneous write operation to the blockof resistive memory cells 500 can be performed by activating cell blockswitching transistors TB using a memory cell block select signal BSL.The cell block switching transistors TB enable a row of resistive memorycells R_(m) to be activated by a signal provided via the respectivebottom electrode signal line BE1-m.

Furthermore, the bitlines BL1-n connected to each of the resistivememory cells in the rows of the block 500 are provided with currentsIBL1-n having directions that are associated with logical data value tobe stored in the individual resistive memory cell in the group selectedfor programming. It will be understood that the signals provided by thebottom electrode signal line 1-m can be coupled onto digit lines DL1-mwhich are used to conduct a current across the group of resistive memorycells R_(m) to be programmed and, further, that the currents provided bythe bitline BL1-n also are conducted across the resistive memory cellsR_(m) to be programmed.

The current provided by the respective digit line DL1-m generates a hardmagnetic field having a direction in each of the resistive memory cellsbased on the direction of the current provided via the digit line.Furthermore, the currents provided via the bitlines, BL1-n generaterespective easy magnetic fields, each having a direction based on thedirection of the current IBL1-n.

In an exemplary write operation shown by FIG. 6, a simultaneous writeoperation can be performed to a group of resistive memory cells C₂included in the block 500. In particular, a current I_(DL) is providedto the digit line DL2 to provide the hard magnetic fields having theorientations shown whereas the individual currents IBL1-n provided viathe respective bitlines BL1-n generate the respective easy magneticfields, each having a direction based on the direction of the respectivecurrent IBL1-IBLn. For example, the easy magnetic field generated in theresistive memory cell C21 has the direction shown based on the directionof the current IBL1 whereas the easy magnetic field generated inresistive memory cell C22 is opposite that generated in C21 based on theopposing direction of the current IBL2.

As further shown in FIG. 6, the easy magnetic field generated in theresistive memory cell C2 n has the same direction as that generated inthe resistive memory cell C21 based on the same direction of the currentIBLn compared to IBL1. It will be understood that the logical data valuestored in each of the resistive memory cells C21-C2 n is based on thecombination of the respective easy and hard magnetic fields generated bythe currents IDL and IBL1-n. A programming mode can be carried out usingthe signal levels shown in FIG. 15 in some embodiments according to theinvention.

FIG. 7 is a block diagram of an MRAM including first and second biasingcircuits 59 a/b and current source transistors TC1-TCi in someembodiments according to the invention. In particular, the first biascircuit 59A provides a first bias voltage to digit lines DL1-mresponsive to activation of transistors TR′ by a row decoder 55. Thefirst bias voltage provided by the bias circuit 59 a can be provided tothe selected block of resistive memory cells BLK1-i through activationof switching transistors TB to couple the bias voltage to the bottomelectrode of the resistive memory cell selected for access. A secondbias voltage can be provided to the resistive memory cells selected foraccess by a bitline driver 57 a/b that drives the bitlines coupled tothe resistive memory cells responsive to a current source/column decoder51 and current sync/column decoder 53.

A second bias circuit 59 b can provide a second bias voltage tounselected memory blocks (i.e., memory blocks which are not to beaccessed during a current read operation) responsive to a row decoder 55through transistors TR′. Accordingly, the second bias circuit 59 b canbe used to apply biasing to otherwise unselected resistive memory cellsto reduce the generation of parasitic currents which may otherwiseaffect currents generated by the biasing of resistive memory cells to beaccessed (thereby reducing the likelihood of read errors).

FIG. 8 is a simplified schematic illustration of a portion 800 of theMRAM 500 shown in FIG. 7 including current source transistors TC in someembodiments according to the invention. In operation, programmingcurrents provided via lines CSL2 and 3 are conducted across resistivememory cells to be programmed while avoiding conducting the programmingcurrent across resistive memory cells that are not to be programmed.

A programming current used to program resistive memory cells Rm includedin a memory block 805 is provided by a current source line CSL2. Thecurrent source line CSL2 is located in a space that separates the memoryblock 805 from adjacent memory block 806, which is not to be programmed.The current used to program the reference cells R_(m) included in theblock 805 is provided by the current source line CSL2 to the currentsource select transistors TC2 enabled by wordlines WL1 and WL2. Theactivation of the current source select transistors TC2 couples theprogramming current from the current source select line CSL2 to thedigit lines DL1 and DL2. The programming current is conducted across thebitlines BL1-BLn adjacent to the resistive memory cells R_(m) includedin the memory block 805.

The current source select transistors TC3 are also enabled via thewordlines WL1 and WL2 to couple the programming current from the digitlines DL1 and DL2 onto the current source line CSL3 that is located in aspace that separates the memory block 805 (being programmed) from anadjacent memory block 807, which is not to be programmed. Theprogramming current is then conducted between the spacing that separatesthe memory block 805 from the memory block 807 to the current sync 53shown in FIG. 7.

Accordingly, the programming current is conducted across the resistivememory cells R_(m) to be programmed while avoiding crossing resistivememory cells that are included in memory blocks that are not to beprogrammed. In particular, the programming currents are conducted in thespaces that separate the block to be programmed from the blocks that arenot programmed substantially parallel to the bitlines. Avoiding crossingresistive memory cells that are not selected for programming can reducethe likelihood that the unselected resistive memory cells can be remainundisturbed by the programming current.

FIG. 9 is a cross sectional view of layers included in a portion of anMRAM corresponding to the portion 800 in FIG. 8 and the cross-sectionI-I′ shown in FIGS. 10-12, which represent plan views and a layoutrespectively in some embodiments according to the invention. Referringto FIG. 9, the cross-section corresponding to the portion 800 shown inFIG. 8 includes a substrate 1 including an oxide layer 5 and isolationlayers 3 used to isolate the cell block switching transistor TB havingsource and drain regions 9S/9D formed in active region 3A. The cellsblock switching transistor also includes a cellblock select line 7Cconnected to a gate electrode thereof.

An interconnect 18 couples the drain 9D of the cellblock switchingtransistor TB to a digit line 19A which can be coupled to a bottomelectrode 25A (separated from the digit line 19A by an interlayerdielectric 21) via the cellblock switching transistor TB. The bottomelectrode 25A is coupled to the resistive memory cells 27 which arein-turn contacted by the bitlines BL1-BLN. The structure of the bottomelectrode, and the resistive memory cells 27 are covered by an upperinterlayer dielectric layer 29.

Still referring to FIGS. 9-12, a first sub-wordline 7A′ and a secondsub-wordline 7A″ are connected to first and second local interconnectlines 13A that is separated from the underlying sub-wordlines 7A and 7A″by an interlayer dielectric 11. First and second current source linesCSL2 and CSL3 are shown as layers 13C and D respectively on theinterlayer dielectric 11 which is also covered by an interlayerdielectric layer 15.

FIG. 13 is a simplified circuit schematic illustrating first and secondbias circuits 59 a and 59 b used to provide different bias voltages toresistive memory blocks BLK1-i in some embodiments according to theinvention. In particular, the first bias circuit 59 a provides and firstbias voltage to a bias line BLN1 that is coupled to the pass transistorsTR′. The pass transistors TR′ are enabled responsive to an output of anenable gate ND1 which is enabled by a read enable signal REN and outputsfrom the row decoder circuit 55.

The second bias circuit 59 b provides a second bias voltage to resistivememory blocks that are not selected for access during a read operation.In particular, the second bias circuit 59 b provides a second biasvoltage via a bias line BLN2 that is provided to unselected memoryblocks via past transistors TR″ that are enabled responsive to enablegates ND2 enabled in response to the read enable signal and invertedoutputs of the row decoder that are analogous to those used to enablethe pass transistors associated with the first bias circuit 59 a. Asshown in FIG. 13, the respective voltages provided by the first andsecond bias circuits 59 a and 59 b can be provided to the respectiveresistive memory blocks across only the single pass transistor TR′/TR″to the digit line (or wordline) coupled to the respective memory block.

FIG. 14 is a high-level block diagram that illustrates systems 1400including MRAM devices according to some embodiments of the invention.In particular, MRAMs can be utilized in a wide variety of systemsincluding, generally, a processor circuit 1001, IO devices 1005, and abus interconnecting these components (as well as other componentsincluded in the system 1400 as well as external components coupledthereto.) The types of systems included in the system 1400 can bepersonal media players, mobile navigation systems, home appliances,personal digital assistance, personal computers, digital cameras,televisions, game consoles, or the like.

As described herein, in some embodiments according to the invention, aresistive memory device can be read by applying a predetermined voltagelevel to a first word line coupled to a first resistive memory cellduring a read operation of a second resistive memory cell that iscoupled to a second wordline. For example, in an operation where a firstgroup of memory cells is to be simultaneously read from a block, a firstvoltage level can be applied to wordlines of memory cells that are notselected for the read operation, whereas a second voltage can be appliedto the wordline that is coupled to the memory cells that are selectedfor the read operation.

Furthermore, the bitlines coupled to the resistive memory cells (bothselected as well as the non-selected) can have the first voltage levelapplied thereto so that the unselected memory cells are substantiallynon-biased due to the fact that the associated bitline and wordline foreach of the unselected memory cells has substantially the same voltageapplied thereto. In contrast, the memory cells that are selected for theread are biased by the different voltages applied to the bitlines andwordlines of the selected memory cells. The non-biasing of theunselected memory cells may avoid the generation of parasitic currentswhich may otherwise increase/decrease the current generated by biasingof the selected memory cells. If unaddressed, the parasitic currentscan, therefore, affect operation of sense amplifier circuits which (ifthe parasitic currents are significant enough) cause errors during theread operation.

In still other embodiments according to the invention, current used toprogram resistive memory cells in a block of the device can be conductedacross a single block of resistive memory cells to be programmed.Accordingly, the programming current may be conducted to the block to beprogrammed by conducting the programming current between adjacent blocksof resistive memory cells to a first current source transistor that islocated on a first opposing side of the block of resistive memory cellsto be programmed. The first current source transistor is used totransfer the programming current from the area between the adjacentblocks of resistive memory cells to across the block of memory cells tobe programmed. Furthermore, a second current source transistor islocated opposite the first current source transistor and is locatedbetween the block of the resistive memory cells to be programmed and afurther adjacent block of resistive memory cells which are not to beprogrammed.

The second current source transistor can conduct the programming currentaway from the block of resistive memory cells to be programmed in thearea that separates the adjacent resistive memory block. Accordingly,conducting the programming currents using the two opposing currentsource transistors allows the programming current to be conducted acrossbitlines in the block of resistive memory cells to be programmed whileavoiding conducting the programming current across bitlines included inadjacent blocks of resistive memory cells that are not to be programmed.Avoiding conducting the programming current across the bitlines ofresistive memory cells that are not to be programmed can reduce thelikelihood of disturbing the data stored in the resistive memory cellswhich are not to be programmed, thereby reducing the likelihood of anerror for a read of the disturbed resistive memory cells.

In other embodiments according to the invention, a resistive memorydevice can include first and second bias circuits that are configured toapply voltage levels to both selected as well as unselected wordlinesduring a read operation. For example, in some embodiments according tothe invention, a first bias circuit can be used to generate a voltagelevel that is applied to the wordlines connected to resistive memorycells that are to be read, whereas a second bias circuit can be used togenerate the second voltage level applied to the wordlines coupled tothe memory cells that are not to be read.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of accessing a resistive memory device comprising: applyinga predetermined voltage level to a first word line coupled to a firstresistive memory cell block during a read operation of a secondresistive memory cell block coupled to a second word line; andconducting programming current via a pair of opposing current sourcetransistors located on first and second opposing sides of the firstblock to conduct the programming current from the first end to thesecond end across bit lines coupled to resistive memory cells in thefirst block and to conduct the programming current parallel to thesecond block.
 2. A method according to claim 1 wherein the predeterminedvoltage level comprises a first voltage level, the method furthercomprising: applying a second voltage level to the second word line,wherein the second voltage level is greater than or less than the firstvoltage level.
 3. A method according to claim 2 further comprising:applying the first voltage level to a bit line coupled to the secondblock.
 4. A method according to claim 1, wherein either the firstvoltage level or the second voltage level is a ground level.
 5. Amagnetic memory cell array device comprising: a first current sourceline extending between pluralities of first and second memory cellsconfigured for respective simultaneous programming and configured toconduct adequate programming current for writing one of the pluralitiesof first and second memory cells; a first current source transistorcoupled to the first current source line and to a word line; aprogramming conductor coupled to the first current source transistor andextending across bit lines coupled to the one of the pluralities offirst and second memory cells, configured to conduct the programmingcurrent across the bit lines; a second current source transistor coupledto the programming conductor and configured to switch the programmingcurrent from the programming conductor to a second current sourcetransistor output; a second current source line extending adjacent theone of the pluralities of first and second memory cells opposite thefirst current source line; a first bias circuit configured to apply afirst bias voltage to the first or second memory cells selected foraccessed during a read operation; and a second bias circuit configuredto apply a second bias voltage to the first or second memory cellsunselected for access during the read operation.
 6. A magnetic memorycell array according to claim 5 further comprising: a bit line drivercircuit configured to provide a third bias voltage to the first orsecond memory cells unselected for access during the read operation, thethird bias voltage being substantially equal to the second bias voltage.7. A magnetic memory cell array according to claim 6 further comprising:first and second pass transistors each coupled between respectiveoutputs of the first and second bias circuits and the first and secondword lines; and first and second enable gates coupled to gates of thefirst and second pass transistors, configured to pass the predeterminedvoltage level from the respective outputs to the first and second wordlines through the pass transistors responsive to outputs of the enablegates.
 8. A magnetic memory cell array according to claim 7 wherein thefirst and second pass transistors each provide a single voltage dropacross respective devices between the outputs and the first word line.9. A magnetic memory cell array according to claim 5, wherein themagnetic memory cell array is included in a personal media player,mobile navigation system, home appliance, personal digital assistance,personal computer, digital camera, television, or game console.
 10. Amagnetic memory cell array according to claim 5, wherein the first andsecond word lines comprises respective first and second digit lines. 11.A method of reading data from a resistive memory device comprising:applying a predetermined voltage level to a first word line coupled to afirst resistive memory cell during a read operation of a secondresistive memory cell coupled to a second word line.
 12. A methodaccording to claim 11 wherein the predetermined voltage level comprisesa first voltage level, the method further comprising: applying a secondvoltage level to the second word line, wherein the second voltage levelis greater than or less than the first voltage level.
 13. A methodaccording to claim 12 further comprising: applying the first voltagelevel to a bit line coupled to the second resistive memory cell.
 14. Amethod according to claim 11 further comprising: applying a voltagelevel that is substantially equal to the predetermined voltage level toa bit line coupled to the first resistive memory cell, wherein the readoperation comprises a single memory cell read operation.
 15. A methodaccording to claim 11 wherein the read operation comprises asimultaneous read operation of a plurality of resistive memory cellscoupled to the second word line.
 16. A method of writing data to aresistive memory device comprising: conducting programming current via apair of opposing current source transistors located on first and secondopposing sides of a block of resistive memory cells to conduct theprogramming current from the first end to the second end across bitlines coupled to the resistive memory cells and to conduct theprogramming current parallel to at least one block of resistive memorycells located adjacent the first or second end.
 17. A method accordingto claim 16 wherein the resistive memory cells comprise magnetic memorycells, PRAM cells, or OxRam cells.
 18. A method of providing programmingcurrent to resistive memory cells during a write operation to aresistive memory device, the method comprising: conducting programmingcurrent across bit lines in a block of resistive memory cells to beprogrammed while avoiding conducting the programming current across bitlines included in adjacent blocks of the resistive memory cells.
 19. Amethod according to claim 18 wherein the resistive memory cells comprisemagnetic memory cells, PRAM cells, or OxRam cells.
 20. A resistivememory device comprising: a pair of opposing current source transistorslocated at respective first and second ends of a block of memory cellsand configured to conduct programming current from the first to thesecond ends across bit lines coupled to the memory cells and configuredto conduct the programming current parallel to adjacent blocks of memorycells.
 21. A method according to claim 20 wherein the resistive memorycells comprise magnetic memory cells, PRAM cells, or OxRam cells.
 22. Aresistive memory device comprising: a bias circuit configured to apply apredetermined voltage level to a first word line coupled to a firstresistive memory cell during a read operation of a second resistivememory cell coupled to a second word line.
 23. A device according toclaim 22, wherein the predetermined voltage level is a ground level. 24.A device according to claim 22, wherein the resistive memory device isincluded in a personal media player, mobile navigation system, homeappliance, personal digital assistance, personal computer, digitalcamera, television, or game console.
 25. A device according to claim 22wherein the bias circuit comprises a first bias circuit, the devicefurther comprising: a second bias circuit configured to apply a secondvoltage level to a word line coupled to the second resistive memorycell, wherein the second voltage level is greater than or less than thefirst voltage level.
 26. A device according to claim 22 furthercomprising: a pass transistor coupled between an output of the biascircuit and the first word line; and an enable gate coupled to a gate ofthe pass transistor, configured to pass the predetermined voltage levelfrom the output to the first word line through the pass transistorresponsive to an output of the enable gate.
 27. A device according toclaim 26 wherein the pass transistor comprises the only voltage dropacross a device between the output and the first word line.
 28. A deviceaccording to claim 22 further comprising: a pass transistor coupled tothe output and configured to provide the output to a drain bias line;and a low switching transistor coupled to the drain bias line andconfigured to provide the output to the first word line responsive to arow address decoder enable signal.
 29. A resistive memory devicecomprising: a first bias circuit configured to apply a first biasvoltage to first or second memory cells selected for accessed during aread operation; and a second bias circuit configured to apply a secondbias voltage to the first or second memory cells unselected for accessduring the read operation.
 30. A resistive memory device having aplurality of cell blocks, each cell block comprising: a plurality ofbitlines; a plurality of bottom electrodes crossing over the bitlines; aplurality of resistive cells being located in cross points of the bottomelectrodes and the bitlines, each of the resistive cells having a firstelectrode coupled to one of the bitlines and has a second electrodecoupled to one of the bottom electrodes; a plurality of digitlinescorresponding to each of the bottom electrodes; a plurality of switchingtransistors being coupled to the digitlines and bottom electrodes; and acell block select line coupled to an input node of the switchingtransistors, wherein at least one digitline is coupled to each cellblock in common.
 31. A device according to claim 30 further comprising:a column decoder being coupled to the cell block select line; and a rowdecoder being coupled to a plurality of the digitlines, the row decoderproviding a selected digitline with a first voltage level and unselecteddigitlines with a second voltage level; and a sense amplifier circuitbeing coupled to the bitlines, the sense amplifier providing theselected bitline with the second voltage level and sensing a currentthrough the selected bitlines.
 32. A device according to claim 31,wherein either the first voltage level or the second voltage level isground level.